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4. Write Disable
The write disable command sets status register WEN to "0" to prohibit unintentional writing. "Figure 8 Write Disable"
shows the timing waveforms. The write disable command consists only of the first bus cycle, and it is initiated by
inputting (04h). The write disable state (WEN "0") is exited by setting WEN to "1" using the write enable command
(06h).
CS
Figure 7 Write Enable
CS
Figure 8 Write Disable
Mode3
0 1 2 3 4 5 6 7
Mode3
0 1 2 3 4 5 6 7
SCK
Mode0
8CLK
SCK
Mode0
8CLK
SI
SO
06h
MSB
High Impedance
SI
SO
04h
MSB
High Impedance
5. Power-down
The power-down command sets all the commands, with the exception of the silicon ID read command and the
command to exit from power-down, to the acceptance prohibited state (power-down). "Figure 9 Power-down" shows
the timing waveforms. The power-down command consists only of the first bus cycle, and it is initiated by inputting
(B9h). However, a power-down command issued during an internal write operation will be ignored. The power-down
state is exited using the power-down exit command (power-down is exited also when one bus cycle or more of the
silicon ID read command (ABh) has been input). "Figure 10 Exiting from Power-down" shows the timing waveforms of
the power-down exit command.
CS
Figure 9 Power-down
Power down
mode
tDP
CS
Figure 10 Exiting from Power-down
Power down
mode
tPRB
Mode3
0 1 2 3 4 5 6 7
Mode3
0 1 2 3 4 5 6 7
SCK
Mode0
8CLK
SCK
Mode0
8CLK
SI
SO
B9h
MSB
High Impedance
SI
SO
ABh
MSB
High Impedance
No.A2096-10/22
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